A cache in a central processing unit is a data storage structure that is used by the central processing unit of a computer to reduce the average time that it takes to access memory. It is a memory which stores copies of data that is located in the most frequently used main memory locations. Moreover, cache memory is memory that is smaller and that may be accessed more quickly than main memory. There are several different types of caches. These include physically indexed physically tagged (PIPT), virtually indexed virtually tagged (VIVT) and virtually indexed physically tagged (VIPT).
Caches that can accommodate multiple accesses in a single cycle provide performance advantages. In particular, such caches feature reduced access latencies. Conventional approaches to accommodating multiple accesses in a single cycle include the use of multi-ported caches and the provision of caches that include a plurality of tag and data banks.
A multi-ported cache is a cache which can serve more than one request at a time. In accessing some conventional caches a single memory address is used, whereas in a multi-ported cache, N memory addresses can be requested at a time, where N is the number of ports that is possessed by the multi-ported cache. An advantage of a multi ported cache is that greater throughput (e.g., a greater number of load and store requests) may be accommodated. However, the number of cache ports that are needed to accommodate increasingly high levels of throughput may not be practical.
Caches that include a plurality of tag and data banks can serve more than one request at a time as each bank can serve at least one request. However, when more than one request attempts to access the same bank, the request that will be allowed to access the bank must be determined. In one conventional approach, serial arbitrations are used to determine which request will be allowed to access the data bank and to access the tag bank for the tag that corresponds to the request. However, the time that it takes to execute such arbitrations can delay access to the bank and thus delay the triggering of the critical Load Hit signal. Moreover, because a plurality of both loads and stores may need to be accommodated, the additional banks, ports and arbitration that may be needed can exact unsatisfactory latency penalties.